Lead AI Accelerator SoC Architect

OHO Group (Lithuania); San Jose (CA); On-site; USD 200,000 - 320,000; Full time

Job summary

OHO Group (Lithuania) invites a Lead ASIC Design Engineer to join a San Francisco Bay Area AI accelerator startup.

You will own RTL design and microarchitecture, collaborating with architecture, verification, software and system teams throughout the silicon development cycle. The role emphasizes high ownership from day one on complex SoCs, interconnects, and performance-critical fabrics.

Qualifications

• 10+ years of ASIC/SoC design experience with hands-on RTL development.
• Experience designing complex SoCs, NoCs, interconnects, fabrics or high-performance processors.
• Familiarity with PCIe, CXL or UCIe.
• Experience with GPUs, AI accelerators, CPUs, TPUs is highly desirable.
• Experience with HBM, memory controllers or coherent fabrics is a strong plus.

Responsibilities

• Own RTL design and microarchitecture.
• Work on cache-coherent and non-coherent interconnects and associated protocols.
• Define and review microarchitectural specifications and translate them into robust, synthesizable RTL.
• Work closely with verification engineers on design validation, debugging and performance analysis.
• Collaborate with architecture, verification, software and system teams throughout the silicon development cycle.

Skills

RTL design

Microarchitecture

NoCs / interconnects

PCIe

CXL

UCIe

AI accelerators

GPUs

Memory controllers

HBM

Coherent fabrics

Education

BS/MS/PhD in EE/CE/CS

Job description

OHO Group (Lithuania) invites a Lead ASIC Design Engineer to join a San Francisco Bay Area AI accelerator startup.

You will own RTL design and microarchitecture, collaborating with architecture, verification, software and system teams throughout the silicon development cycle. The role emphasizes high ownership from day one on complex SoCs, interconnects, and performance-critical fabrics.