Senior RTL Design Engineer for AI Accelerator Chips

Energy Jobline ZR; Sonoma (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

Energy Jobline ZR is seeking a Senior RTL Design Engineer for accelerator startups in the San Francisco Bay Area. You will own your design work in a small, high‑caliber team, collaborating closely with physical design, verification and leadership to push AI accelerator technology.

You’ll lead end‑to‑end projects across the full chip lifecycle, work with industry leaders from top semiconductor companies, and develop into a leadership role with equity upside as the company grows.

Qualifications

• Strong experience across ASIC and SoC design principles.
• Broad understanding of the wider elements of chip design.
• Hands-on in a fast-moving, high-ownership startup environment.
• Experience with AI/LLM systems and memory/fabric interconnect is a plus, with familiarity of high-speed protocols.

Responsibilities

• Own design work from concept to implementation in collaboration with senior team members.
• Lead end-to-end projects and work across the full chip lifecycle with cross-functional teams.
• Develop into a leadership role with potential equity upside as the company grows.
• Contribute to democratising and innovating AI accelerator technology in a startup setting.

Skills

ASIC design

SoC design

High-speed protocols

Startup environment

Job description

Energy Jobline ZR is seeking a Senior RTL Design Engineer for accelerator startups in the San Francisco Bay Area. You will own your design work in a small, high‑caliber team, collaborating closely with physical design, verification and leadership to push AI accelerator technology.

You’ll lead end‑to‑end projects across the full chip lifecycle, work with industry leaders from top semiconductor companies, and develop into a leadership role with equity upside as the company grows.