AI Accelerator RTL Design Engineer — Equity + Relocation

River AI; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health benefits

Dental benefits

Vision benefits

Unlimited PTO

Relocation support

Job summary

River AI is hiring an exceptional RTL design engineer to architect and implement high-performance AI accelerator SoCs. You will own architecture, micro-architecture, and RTL, collaborating with verification, physical designers, and software teams to optimize PPA and deliver scalable silicon.

You will work across the stack with compiler and performance models, tackling complex design challenges on advanced process nodes, with a focus on power-efficient data paths and high throughput.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering, 5+ years of industry experience.
• Hands-on RTL, synthesis, physical design, and timing tools experience (SystemVerilog, VCS/Verdi, Fusion Compiler, PrimeTime).
• Expert knowledge in Computer Architecture of SoCs, CPUs, GPUs, or AI accelerators.
• Proven track record delivering silicon at scale with ECOs and reliability.
• Collaborative mindset to push boundaries and co-design with engineers.

Responsibilities

• Create high-level architectural specifications and detailed micro-architectures for AI hardware subsystems.
• Design and implement RTL using SystemVerilog, optimizing throughput, latency, and power.
• Work with backend on synthesis, floorplanning, and STA to meet target frequencies.
• Collaborate with compiler, performance modeling, and software teams to identify bottlenecks from ISA to applications.

Skills

RTL design

SystemVerilog

Synthesis

Physical design

Timing analysis

Architecture

C/C++

Python

NoC protocols

Education

B.S. in EE/CE

Tools

VCS/Verdi

Fusion Compiler

PrimeTime

Job description

River AI is hiring an exceptional RTL design engineer to architect and implement high-performance AI accelerator SoCs. You will own architecture, micro-architecture, and RTL, collaborating with verification, physical designers, and software teams to optimize PPA and deliver scalable silicon.

You will work across the stack with compiler and performance models, tackling complex design challenges on advanced process nodes, with a focus on power-efficient data paths and high throughput.