Staff/Principal RTL Design Engineer for AI Inference ASIC

Acceler8 Talent; San Francisco (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Acceler8 Talent is seeking a hands-on Staff, Senior Staff, or Principal RTL Design Engineer for a seed AI hardware startup building a dedicated LLM inference ASIC. You will own a substantial RTL scope and translate microarchitecture into synthesizable RTL, collaborating with verification and physical-design teams near Palo Alto.

Strong Verilog/SystemVerilog skills are essential; AI accelerator or inference ASIC experience is preferred, with deep digital-silicon know-how and a proven track record

Qualifications

• Strong Verilog or SystemVerilog skills are essential.
• AI accelerator or inference ASIC experience is preferred, with strong adjacent digital-silicon experience also relevant.
• Hands-on experience delivering substantial ASIC or SoC RTL.

Responsibilities

• Translate microarchitecture into synthesizable RTL, with ownership of a substantial design scope.
• Design and debug datapaths, control logic and block interfaces.
• Collaborate with verification and physical-design engineers to resolve issues and tapeout readiness.

Skills

RTL design

Verilog/SystemVerilog

ASIC/SoC RTL delivery

Digital silicon design

Tools

EDA tools

Job description

Acceler8 Talent is seeking a hands-on Staff, Senior Staff, or Principal RTL Design Engineer for a seed AI hardware startup building a dedicated LLM inference ASIC. You will own a substantial RTL scope and translate microarchitecture into synthesizable RTL, collaborating with verification and physical-design teams near Palo Alto.

Strong Verilog/SystemVerilog skills are essential; AI accelerator or inference ASIC experience is preferred, with deep digital-silicon know-how and a proven track record