Staff Physical Design Engineer for AI Accelerator SoCs

River; Palo Alto (CA); On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, vision benefits

Unlimited PTO

Relocation support

Job summary

River is seeking exceptional physical design engineers to transform architectural concepts into production-ready silicon for our AI accelerator. You will own the physical implementation flow from synthesis through tape-out and collaborate closely with RTL designers to ensure robust timing, electricals, and verification.

You will push the absolute limits of advanced foundry nodes, optimize layout topologies to maximize density, and contribute to next-generation AI-driven design workflows.

Qualifications

• Bachelor’s degree in Electrical Engineering or Computer Engineering with 5+ years of industry experience in advanced process nodes (7nm or below).
• Hands-on proficiency with PD tools (Innovus, Fusion Compiler, PrimeTime, RedHawk).
• Ability to debug timing, congestion, and power density using first-principles approaches.

Responsibilities

• Drive synthesis and place-and-route from RTL to tape-out.
• Maximize PPA by optimizing layout and PDN for high frequency on advanced nodes.
• Close timing and electricals, including STA, SI, EM, and IR-drop constraints.
• Execute physical verification (DRC, LVS, antenna checks).
• Co-design with RTL to provide early physical feedback on logic and routing.
• Advance flow automation with AI-driven EDA tools to accelerate closure.

Skills

Physical design

Timing closure

Debugging

RTL collaboration

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

Innovus

Fusion Compiler

PrimeTime

RedHawk

Job description

River is seeking exceptional physical design engineers to transform architectural concepts into production-ready silicon for our AI accelerator. You will own the physical implementation flow from synthesis through tape-out and collaborate closely with RTL designers to ensure robust timing, electricals, and verification.

You will push the absolute limits of advanced foundry nodes, optimize layout topologies to maximize density, and contribute to next-generation AI-driven design workflows.