Lead Physical Design for AI Accelerator SoCs

Amazon Web Services (AWS); Austin (TX); On-site; USD 241,000 - 326,000; Full time

Job summary

Annapurna Labs in Austin, Texas, seeks a Senior Manager of Physical Design Engineering to build and lead a world-class PD team delivering multi-billion-transistor ML accelerator SoCs on the latest process nodes. You will own the PD strategy across Inferentia, Trainium, and future products, drive PPA targets, and mentor engineers through tapeouts and cross-functional programs.

This role collaborates with foundries and EDA partners to optimize RTL-to-GDS flows and implement AI/ML-assisted design

Qualifications

• 5+ years people management leading PD teams of 8+ engineers, including hiring, performance management, and organizational growth.
• 10+ years hands‑on ASIC/SoC physical design across multiple advanced nodes (7nm, 5nm, 3nm) with multiple successful tapeouts.
• Technical depth across full RTL-to-GDSII: floorplanning, CTS, routing, timing closure, PDN design, IR‑drop/EM signoff, physical verification, and tapeout.
• Mastery of both EDA ecosystems: Synopsys (Fusion Compiler/ICC2, PrimeTime, StarRC, RedHawk-SC) AND Cadence (Innovus, Tempus, Quantus, Voltus). Physical verification with Siemens Calibre (DRC, LVS, PERC).
• Deep expertise in advanced STA (MMMC, POCV/AOCV, SSTA, PBA, IR‑aware timing) and power integrity (static/dynamic IR‑drop, EM, rush current, Ldi/dt, package‑aware analysis).
• Proven expertise in high‑speed PD (multi‑Ghz datapaths, SerDes, DDR5, HBM, PCIe Gen5+, UCIe) and low‑power design (UPF, power gating, DVFS, retention).
• Experience with hierarchical methodologies for very large SoCs (>1B transistors).
• Expert scripting in TCL, Python, Perl.

Responsibilities

• Build, hire, and develop a physical design team of 10-15 engineers. Own headcount planning, performance management, career growth, and organizational scaling to support multiple concurrent tapeouts.
• Own the physical design strategy and execution roadmap across Inferentia, Trainium, and future products: implementation architecture, hierarchical methodology, PPA target-setting, and technology node adoption.
• Institutionalize continuous PPA improvement: benchmarking frameworks, regression tracking, design-quality dashboards, post-tapeout retrospectives, and structured improvement programs that compound across generations.
• Provide hands‑on technical leadership on the hardest problems: multi‑GHz timing closure, PDN architecture, high-speed I/O physical design, and 2.5D / 3D cross-die integration.
• Lead technology node enablement for 2nm and beyond: PDK evaluation, reference flow development, PPA pathfinding, and adoption recommendations.
• Define and deploy innovative RTL2GDS methodologies and CAD flows. Champion AI/ML-augmented design automation (RL-placement, ML-guided ECO, predictive analytics). Optimize cloud infrastructure for PD compute.
• Serve as part of senior technical interface with foundry partners and EDA vendors on tool roadmap, co-development, and technology co-optimization.
• Own tapeout execution: readiness reviews, foundry submittal, mask data coordination, and post-silicon yield learning. Drive cross-functional alignment with RTL, DFT, STA, Package, and Validation teams.

Skills

People management

ASIC/SoC PD

RTL-to-GDSII

PPA optimization

2nm+ experience

EDa tools (Synopsys/Cadence)

2.5D/3D integration

Scripting (TCL/Python)

Tools

Fusion Compiler/ICC2

Innovus/Tempus

Calibre

Job description

Annapurna Labs in Austin, Texas, seeks a Senior Manager of Physical Design Engineering to build and lead a world-class PD team delivering multi-billion-transistor ML accelerator SoCs on the latest process nodes. You will own the PD strategy across Inferentia, Trainium, and future products, drive PPA targets, and mentor engineers through tapeouts and cross-functional programs.

This role collaborates with foundries and EDA partners to optimize RTL-to-GDS flows and implement AI/ML-assisted design