AI Accelerator Verification Engineer: RTL & Emulation

RosaicLabs Inc; California; On-site; USD 140,000 - 240,000; Full time

Benefits offered by this job

Medical benefits (incl. HSA)

Dental, Vision

Life & AD&D, 401(k)

Job summary

RosacLabs Inc. is seeking an AI Accelerator Design verification engineer to own verification environments from test plan to coverage closure and SI bring‑up. You will work on tensor processing, on‑chip networks, and SoC flows in a hands‑on role.

Responsibilities include building synthesizable testbenches, running RTL/emulation co‑simulations, and applying formal verification methods. A strong background in AI accelerators and digital design is required, with collaboration across RTL, CAD, and

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
• Strong foundation in AI accelerator and computer architecture and digital design.
• Familiarity with ISA simulators or reference models.
• Hands-on experience using agentic AI tools across the engineering workflow.
• Proficiency in SystemVerilog, C/C++, and assembly is desirable.

Responsibilities

• Develop verification plans for AI accelerator blocks: tensor processing, fabric / network-on-chip, and SoC flows.
• Write and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models.
• Build emulation-friendly testbenches: synthesizable environments for simulation and emulation.
• Use agentic AI tools to generate test plans, write tests, triage regressions, and review results.
• Verify numerical correctness of compute datapaths against bit-accurate models.
• Run real ML kernels and random programs on RTL co-simulated with a reference model.
• Define and drive functional and code coverage goals to closure.
• Debug RTL/testbench and coordinate with RTL designers to root-cause bugs.
• Apply formal verification, assertions (SVA), and emulation where appropriate.
• Run and maintain regressions across simulation, emulation, and FPGA platforms.
• Collaborate with RTL design, performance modeling, CAD/methodology, and software teams on strategy.
• Participate in microarchitecture, RTL, and verification reviews; write technical docs.

Skills

SystemVerilog/UVM

C/C++

Python

Tcl/Rust scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering or CS

Tools

SystemVerilog

UVM

Emulation/FPGA prototyping

Job description

RosacLabs Inc. is seeking an AI Accelerator Design verification engineer to own verification environments from test plan to coverage closure and SI bring‑up. You will work on tensor processing, on‑chip networks, and SoC flows in a hands‑on role.

Responsibilities include building synthesizable testbenches, running RTL/emulation co‑simulations, and applying formal verification methods. A strong background in AI accelerators and digital design is required, with collaboration across RTL, CAD, and