CPU Custom Library and Memory Layout Lead

Nuvacore; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Nuvacore is seeking a Custom Library and Memory Layout Lead to drive layout for high-performance CPU designs in Santa Clara. You will lead layout of custom library cells and memory arrays, own end-to-end closure, and collaborate with foundry, CAD, and circuit teams to ensure PPA targets are met.

You will define layout methodologies, build automation, and manage external vendors to scale layouts across macro designs.

Qualifications

• BS or MS with 12+ years in custom/standard-cell and/or memory layout at advanced CMOS nodes.
• Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays.
• Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and LVSC closure using industry-standard EDA tools.
• Strong understanding of layout-dependent effects, matching, and symmetry techniques and impact on PPA.
• Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.

Responsibilities

• Lead physical layout of custom library cells and memory arrays at advanced nodes.
• Own end-to-end layout closure: floorplanning, place-and-route, DRC/LVS cleanup, and extraction hand-off.
• Collaborate with circuit design, foundry, CAD, and DFT teams to optimize layout for PPA and yield.
• Define and drive layout automation and best practices, including script-based generation and regression flows.
• Manage layout vendors and contractors, scoping work, and reviewing deliverables for PPA and compliance.

Skills

Layout engineering

PPA optimization

EDA collaboration

Automation scripting

Education

BS/MS in Electrical Engineering

Tools

Virtuoso

Calibre

StarRC

Job description

Nuvacore is building ground-up high performance, low-power CPU for next-generation compute workloads. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

As a Custom Library and Memory Layout Lead, you will participate in the following :

• Lead physical layout of custom library cells (flip-flops, clock-gating cells, level shifters, AOI cells) and custom memory arrays (bit cell arrays, sense amps, decoders, register files) at advanced process nodes - own layout prototyping of critical cells.
• Own end-to-end layout closure: floorplanning, logic/SRAM place-and-route, DRC/LVS/antenna clean-up, parasitic extraction hand-off, and mitigation of layout-dependent effects (LDE).
• Partner with circuit design, Foundry/PDK, CAD, and DFT teams to co-optimize layout for PPA, manufacturability, and yield; validate IP on testchips.
• Define and drive layout methodology and automation — including P-cell/script-based layout generation and DRC/LVS regression — to raise design efficiency and set team-wide best practices.
• Manage layout vendors and contractors to scale layout execution across macro designs and cells — scoping work packages, setting quality/schedule targets, and reviewing deliverables for PPA, DRC/LVS, and methodology compliance.

MINIMUM QUALIFICATIONS

• Hold a BS or MS degree with 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.
• Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays — bit cells, sense amps, decoders — at advanced CMOS nodes.
• Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard EDA tools (e.g. Virtuoso, Calibre, StarRC).
• Strong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit PPA and variation.
• Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.
• Strong communication and collaboration skills, comfortable working directly with circuit design, foundry, and CAD partner teams.
• Relevant hands-on experience laying out designs in cutting-edge process technologies, preferably Gate-All-Around (GAA) nodes.

REQUIREMENTS — PREFERRED

• Experience across the full custom layout flow — floorplanning, cell/bit-cell layout, P-cell/script-based automation, DRC/LVS signoff, and extraction hand-off.
• Proficient in SKILL, Python, or Tcl to build and improve layout automation and DRC/LVS regression flows.
• Track record delivering production-level standard cell and/or memory layouts through tape-out, with silicon-validated PPA in high-volume products.
• Experience with testchip layout development and DTCO partnering with foundries at leading-edge nodes.
• Experience managing external layout vendors/contractors — work scoping, quality/schedule tracking, and technical review — to scale capacity across macro and cell layout programs.
• Experience using Agentic AI tools for productivity and automation.

$200,000 - $300,000 a year