IC Layout Designer

Avicena Tech; Sunnyvale (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Avicena Tech in Sunnyvale, CA is seeking an experienced IC Layout Designer to support the physical layout of analog, mixed-signal, and high-speed ICs. You will translate schematics into manufacturable layouts, ensuring matching, parasitic, reliability and manufacturability per foundry rules.

Candidates should have CADENCE Virtuoso layout experience, DRC/LVS tooling (Calibre/ Pegasus/ Assura), and a strong grasp of CMOS layout techniques, device matching, floorplanning, and parasitic extraction

Qualifications

• Associate or bachelor’s degree in electrical engineering, microelectronics, or related field.
• Experience with IC layout tools such as Cadence Virtuoso Layout Suite.
• Solid understanding of CMOS device layout and process layers.
• Experience running and debugging DRC/LVS using Calibre, Assura, Pegasus, or similar.
• Ability to read and understand circuit schematics.
• Strong attention to detail and ability to follow layout guidelines.
• Knowledge of parasitic effects, device matching, shielding, and signal integrity.
• Good communication skills and ability to work with circuit designers.

Responsibilities

• Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.
• Work from circuit schematics to create clean, compact, and manufacturable layouts.
• Layout devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.
• Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.
• Run and debug physical verification checks including DRC, LVS, ERC, antenna checks, density checks, and reliability checks.
• Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.
• Support layout floorplanning, block-level integration, and top-level chip assembly.
• Follow foundry design rules and process-specific layout guidelines.
• Work with design engineers to optimize layout for performance, area, power, yield, and reliability.
• Prepare layout databases for tapeout and support final verification signoff.

Skills

Cadence Virtuoso

DRC / LVS / ERC

Calibre / Pegasus / Assura

Analog layout

Mixed-signal layout

CMOS layout

Device matching

Parasitic extraction

Shielding and isolation

Floorplanning

Top-level integration

Tapeout support

Education

Bachelor’s degree in Electrical Engineering or related field

Tools

Cadence Virtuoso Layout Suite

Calibre

Pegasus

Assura

Job description

Job Description

We are looking for an experienced IC Layout Designer to support the physical layout of analog, mixed-signal, and high-speed integrated circuits. The candidate will work closely with circuit designers to convert schematics into high-quality layouts that meet electrical, matching, parasitic, reliability, and manufacturability requirements. The role requires strong knowledge of CMOS layout techniques, device matching, floorplanning, routing, DRC/LVS/debug, parasitic extraction, and layout best practices for advanced semiconductor processes.

Responsibilities

• Design and implement transistor-level IC layouts for analog, mixed-signal, and high-speed circuits.
• Work from circuit schematics to create clean, compact, and manufacturable layouts.
• Perform layout of devices such as MOSFETs, resistors, capacitors, diodes, guard rings, ESD structures, and interconnect routing.
• Apply layout techniques for device matching, common-centroid structures, shielding, symmetry, dummy devices, isolation, and noise reduction.
• Run and debug physical verification checks including DRC, LVS, ERC, antenna checks, density checks, and reliability checks.
• Perform parasitic extraction and work with circuit designers to reduce unwanted resistance, capacitance, coupling, and mismatch.
• Support layout floorplanning, block-level integration, and top-level chip assembly.
• Follow foundry design rules and process-specific layout guidelines.
• Work with design engineers to optimize layout for performance, area, power, yield, and reliability.
• Prepare layout databases for tapeout and support final verification signoff.

Required Qualifications

• Associate degree, bachelor’s degree, or equivalent experience in electrical engineering, microelectronics, or a related field.
• Experience with IC layout tools such as Cadence Virtuoso Layout Suite.
• Good understanding of CMOS device layout and semiconductor process layers.
• Experience running and debugging DRC/LVS using tools such as Calibre, Assura, Pegasus, or similar.
• Ability to read and understand circuit schematics.
• Strong attention to detail and ability to follow layout guidelines.
• Understanding of parasitic effects, device matching, shielding, and signal integrity.
• Good communication skills and ability to work closely with circuit designers.

Preferred Qualifications

• Experience with analog or mixed-signal blocks such as PLLs, ADCs, DACs, SerDes, bandgaps, regulators, amplifiers, oscillators, filters, or high-speed I/O.
• Experience with advanced CMOS nodes such as 28 nm, 16 nm, 12 nm, 7 nm, or similar.
• Knowledge of FinFET layout rules and advanced-node restrictions.
• Experience with top-level integration, power routing, ESD planning, and chip finishing.
• Familiarity with electromigration, IR drop, latch-up prevention, and reliability rules.
• Experience with layout automation, SKILL scripting, or Python is a plus.

Key Skills

• Cadence Virtuoso
• DRC / LVS / ERC
• Calibre / Pegasus / Assura
• Analog layout
• Mixed-signal layout
• CMOS layout
• Device matching
• Parasitic extraction
• Shielding and isolation
• Floorplanning
• Top-level integration
• Tapeout support