(Mid/Sr/Staff/Princ) Layout Design Engineer (FinFETs/5/7/12/16nm)

Thrive Recruitment Agency; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A technology recruitment firm is seeking an experienced Layout Design Engineer to contribute to advanced mixed-signal layout for low-power, high-speed products. The ideal candidate will have 5-10+ years of layout design experience in deep nanometer FinFET technologies. Responsibilities include layout design, participating in performance analysis, and assisting with floor planning. This role offers the opportunity to join a collaborative team making a significant impact on product development in California.

Qualifications

• 5-10+ years of hands-on layout design experience required.
• Experience with deep nanometer Fin-FET node process is necessary.
• Good understanding of analog and mixed-signal layout fundamentals is essential.

Responsibilities

• Design layout for analog and mixed-signal macros in FinFET technologies.
• Participate in post-layout circuit performance analysis.
• Assist with floor planning and verifying against design rules.

Skills

Layout design of analog and mixed-signal macros

Planning and implementing block-level floor-planning

Power distribution network design

Clock and signal routing

Tools

Cadence tools

DRC and LVS tools

Job description

Job Openings (Mid/Sr/Staff/Princ) Layout Design Engineer (FinFETs/5/7/12/16nm)

About the job (Mid/Sr/Staff/Princ) Layout Design Engineer (FinFETs/5/7/12/16nm)

In this position you will play a key role in contributing to the development of advanced mixed-signal layout for low-power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low-power consumer SOCs.

You will join a highly collaborative team, and your success will have a significant impact on our products

ESSENTIAL DUTIES AND RESPONSIBILITIES:

• Layout design of analog and mixed-signal macros in deep nanometer-level FinFET technologies
• Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed-signal transistor level layout
• DRC, LVS, and other physical verification tools
• Participate in post-layout circuit performance analysis
• Perform physical layout for custom structures in state-of-the-art nanometer-level CMOS technologies using Cadence tools.
• Assist in taking part in floor planning, custom layout, and verifying against design rules and schematics.
• Learn and ramp on new tools and methodologies
• Develop a realistic schedule for block-level layout including complete verifications

QUALIFICATIONS:

• At least 5-10+ years of hands-on layout design experience
• Experience in layout for deep nanometerFin-FET nodesprocess, including block layouts from scratch.
• Good understanding of clock routing and shielding
• Good understanding of analog and mixed-signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating