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Meta's Infrastructure Silicon team seeks an ASIC Implementation Engineer specializing in timing to drive static timing analysis and timing closure across complex SoCs for data center applications.
You will develop SDC constraints, perform sign-off timing, and guide placement, routing, and clock tree synthesis to meet targets.
2+ years ASIC timing experience, PrimeTime and SystemVerilog proficiency, plus scripting (Python/Tcl/Perl). Based in Sunnyvale, CA.
Meta's Infrastructure Silicon team seeks an ASIC Implementation Engineer specializing in timing to drive static timing analysis and timing closure across complex SoCs for data center applications.
You will develop SDC constraints, perform sign-off timing, and guide placement, routing, and clock tree synthesis to meet targets.
2+ years ASIC timing experience, PrimeTime and SystemVerilog proficiency, plus scripting (Python/Tcl/Perl). Based in Sunnyvale, CA.