ASIC Engineer, Implementation - Timing

Meta Careers; Austin (TX); On-site; USD 114,000 - 172,000; Full time

Job summary

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to drive static timing analysis and timing closure across complex SoCs for data center applications.

You will develop timing constraints, run sign-off STA with PrimeTime, collaborate with physical design, and contribute to timing libraries and automation. This role is based in Austin, TX with competitive compensation, bonus, and equity.

Qualifications

• 2+ years of ASIC implementation experience focused on static timing analysis and timing closure.
• Experience with industry-standard STA and sign-off tools such as PrimeTime.
• Experience developing and validating SDC timing constraints for complex SoC designs.
• Ability to script timing analysis and reporting flows using Python, Tcl or Perl.

Responsibilities

• Develop and maintain timing constraints (SDC) for complex SoC designs.
• Perform static timing analysis to identify setup/hold violations and clock skew.
• Drive timing closure with physical design teams for timing targets.
• Analyze timing paths across clock domains and suggest RTL or layout optimizations.
• Generate and validate timing reports for sign-off across corners and OCV.
• Maintain timing exception methodologies and waiver processes.
• Develop timing closure scripts and automation to improve efficiency.

Skills

Static timing analysis

Timing closure

Scripting (Python, Tcl, Perl)

Tools

PrimeTime

Job description

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to help design and deliver custom silicon for data center applications. In this role, you will drive static timing analysis and timing closure across complex System on Chip designs, working at the intersection of front-end and back-end implementation to ensure our infrastructure chips meet performance, power, and area targets at advanced process nodes.ASIC Engineer, Implementation - Timing Responsibilities:Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false pathsPerform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocksDrive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targetsAnalyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizationsGenerate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysisDevelop and maintain timing exception methodologies and waiver processes in coordination with design and verification teamsContribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatabilityInterface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IPSupport design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validationMinimum Qualifications:2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closureExperience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalentExperience developing and validating SDC timing constraints for complex SoC or IP designsExperience with logic synthesis tools and timing-driven optimization techniquesExperience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flowsPreferred Qualifications:Experience with RTL design or synthesis using SystemVerilog or other hardware description languagesExperience with timing closure at advanced process nodes (7nm or below), including on-chip variation and multi-corner multi-mode analysisFamiliarity with physical design concepts such as placement, routing, and parasitic extraction as they relate to timing closureExperience with clock tree synthesis and clock network optimization in the context of timing sign-offAbout Meta:Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].$114,000/year to $172,000/year + bonus + equity + benefitsIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.