Frontend ASIC Implementation & Static Verification Specialist

Meta; Sunnyvale (CA); On-site; USD 114,000 - 172,000; Full time

Job summary

Meta is hiring ASIC Frontend Implementation Engineers in our Infrastructure organization. You will work on front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient SoC IP for data center applications.

Responsibilities include clock and reset domain checks, RTL DFT analysis, creating automation scripts, and collaborating with Design, DV, and Emulation teams to deliver timing-accurate netlists.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field; degree completed before joining Meta.
• 2+ years of experience in static verification tools.
• Experience with Lint, Clock Domain Crossing and Reset Domain crossing.
• Experience with SOC CDC signoff.
• Knowledge of SOC Integration (Clocking, Reset, PLL).
• Knowledge of front-end ASIC flows.
• Experience with RTL design using SystemVerilog or other HDL.
• Experience communicating across internal teams and vendors.

Responsibilities

• Perform Flat and Hierarchical Clock Domain Crossing analysis and sign off CDC with designers.
• Perform Flat and Hierarchical Reset Domain crossing checks and develop reset sequences.
• Perform RTL Lint and create waivers with designers.
• Perform RTL DFT analysis and improve DFT coverage for stuck-at faults.
• Run logic/physical synthesis and generate optimized gate-level netlists.
• Develop automation scripts and methodology for FE-tools (Lint, CDC, RDC).
• Collaborate with Design, DV, and Emulation teams and provide timing/congestion feedback.

Skills

SystemVerilog

RTL design

CDC analysis

Lint tools

DFT analysis

Scripting

Education

Bachelor's degree in Computer Science or Computer Engineering

Tools

Design Compiler

Spyglass

PrimeTime

Formality

Job description

Meta is hiring ASIC Frontend Implementation Engineers in our Infrastructure organization. You will work on front-end implementation from RTL to netlist, including RTL Lint, CDC analysis, timing constraints, and synthesis to build efficient SoC IP for data center applications.

Responsibilities include clock and reset domain checks, RTL DFT analysis, creating automation scripts, and collaborating with Design, DV, and Emulation teams to deliver timing-accurate netlists.