Senior Timing Methodology Lead for FPGA/ASIC

Altera Corporation; San Jose (CA); Hybrid; USD 187,000 - 270,000; Full time

Job summary

Altera, located in San Jose, CA, seeks a senior Design Automation engineer focused on Static Timing Analysis and timing modeling for ASIC/IP/FPGA timing flows. You will lead a small team, own production‑grade flows, and drive cross‑functional engagements with design teams and external vendors.

The role emphasizes greenfield characterization, mentoring engineers, and delivering timing sign-off in a unified flow, with AI/ML-infused automation and strong Python/Tcl scripting background required.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years in semiconductor design automation, CAD/EDA, ASIC/custom IC design, or related field.
• 10+ years with Static Timing Analysis (STA) and timing sign-off methodology.
• 10+ years with industry-standard timing analysis, cell characterization, and/or SPICE tools.
• 10+ years developing automation and software for engineering workflows (Python, Tcl, shell).
• Experience owning and releasing production DA/CAD flows including deployment and maintenance.
• Technical leadership in design automation or timing domain and mentoring engineers.

Responsibilities

• Own and release production-grade DA/CAD flows and timing sign-off.
• Mentor engineers and set methodology direction across teams.
• Collaborate with ASIC, physical design, reliability, and EDA vendors to drive roadmaps.
• Build and maintain training and documentation for timing methodologies.
• Bridge transistor-level simulation through timing models and FPGA timing deliverables.

Skills

STA knowledge

Python

Tcl

Shell scripting

Leadership

Education

Bachelor's degree in Electrical Engineering/Computer Engineering/CS

Master's or PhD preferred

Tools

CAD/EDA tools

Liberty model generation

SPICE simulation

Job description

Altera, located in San Jose, CA, seeks a senior Design Automation engineer focused on Static Timing Analysis and timing modeling for ASIC/IP/FPGA timing flows. You will lead a small team, own production‑grade flows, and drive cross‑functional engagements with design teams and external vendors.

The role emphasizes greenfield characterization, mentoring engineers, and delivering timing sign-off in a unified flow, with AI/ML-infused automation and strong Python/Tcl scripting background required.