ASIC Engineer, Implementation - Timing

RiseMe; Sunnyvale (TX); On-site; USD 114,000 - 172,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Infrastructure Silicon team seeks an ASIC Implementation Engineer specializing in timing to drive static timing analysis and timing closure across complex SoCs for data center applications.

You will develop SDC constraints, perform sign-off timing, and guide placement, routing, and clock tree synthesis to meet targets.

2+ years ASIC timing experience, PrimeTime and SystemVerilog proficiency, plus scripting (Python/Tcl/Perl). Based in Sunnyvale, CA.

Qualifications

• Bachelor's degree in CS/CE or equivalent required.
• 2+ years of ASIC implementation experience with timing analysis.
• Experience with SDC timing constraints and sign-off tools.

Responsibilities

• Develop and maintain SDC timing constraints for complex SoCs.
• Perform static timing analysis to resolve setup/hold violations.
• Drive timing closure with physical design on placement, routing, and clock tree synthesis.
• Analyze timing paths across clock domains and propose RTL or physical optimizations.
• Generate timing reports for sign-off across corners including on-chip variation.
• Develop timing exception methodologies with design and verification teams.
• Create timing automation scripts to improve efficiency.

Skills

Static timing analysis

Timing closure

Python scripting

Tcl scripting

Perl scripting

SystemVerilog

PrimeTime

Clock domain crossing

Education

Bachelor's degree in Computer Science/Engineering or related

Tools

PrimeTime

RTL SystemVerilog

Job description

Meta's Infrastructure Silicon team is seeking an ASIC Implementation Engineer specializing in timing to help design and deliver custom silicon for data center applications. In this role, you will drive static timing analysis and timing closure across complex System on Chip designs, working at the intersection of front-end and back-end implementation to ensure our infrastructure chips meet performance, power, and area targets at advanced process nodes.

Responsibilities

• Develop and maintain timing constraints (SDC) for complex SoC designs, including clock definitions, input/output delays, multicycle paths, and false paths
• Perform static timing analysis using industry-standard sign-off tools to identify and resolve setup, hold, and clock skew violations across hierarchical design blocks
• Drive timing closure through collaboration with physical design engineers, providing guidance on placement, routing, and clock tree synthesis to meet timing targets
• Analyze and debug timing paths across multiple clock domains, identifying critical paths and recommending RTL or physical implementation optimizations
• Generate and validate timing reports for sign-off across process, voltage, and temperature corners, including on-chip variation analysis
• Develop and maintain timing exception methodologies and waiver processes in coordination with design and verification teams
• Contribute to the development and improvement of timing closure scripts and automation flows using scripting languages to increase efficiency and repeatability
• Interface with foundry and library teams to characterize and integrate timing libraries, including standard cells, memories, and hard IP
• Support design handoff between front-end and back-end teams by providing timing-aware synthesis netlists and constraint validation

Minimum Qualifications

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
• Currently has a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• 2+ years of experience in ASIC implementation with a focus on static timing analysis and timing closure
• Experience with industry-standard static timing analysis and sign-off tools such as PrimeTime or equivalent
• Experience developing and validating SDC timing constraints for complex SoC or IP designs
• Experience with logic synthesis tools and timing-driven optimization techniques
• Experience scripting in Python, Tcl, or Perl to automate timing analysis and reporting flows

Preferred Qualifications

• Experience with RTL design or synthesis using SystemVerilog or other hardware description languages
• Experience with timing closure at advanced process nodes (7nm or below), including on-chip variation and multi-corner multi-mode analysis
• Familiarity with physical design concepts such as placement, routing, and parasitic extraction as they relate to timing closure
• Experience with clock tree synthesis and clock network optimization in the context of timing sign-off

$114,000/year to $172,000/year + bonus + equity + benefits