ASIC Timing Closure Engineer (SoC)

Apple; Cupertino (CA); On-site; USD 149,000 - 195,000; Full time

Job summary

Apple in Cupertino, California is seeking an experienced ASIC Timing Engineer to drive timing closure for high-end mobile SoCs. You will develop timing constraints and coverage analysis, and create scripts for critical path analysis, working across RTL, synthesis, and physical implementation.

The role emphasizes collaboration with multiple teams to resolve timing issues and maintain robust timing methodologies and flows throughout the project lifecycle.

Qualifications

• Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
• Experience with digital circuits including combinational and sequential logic.
• Familiarity with RTL (Verilog or VHDL) for debugging timing violations and linking to RTL code.

Responsibilities

• Work on timing closure for ASICs in deep sub-micron processes.
• Develop and enhance timing constraints and coverage analysis for SoC.
• Create and maintain timing verification scripts and checks.
• Collaborate with cross-functional teams on timing issues across RTL, synthesis and physical implementation.

Skills

Digital electronics

FSM design

RTL design (Verilog/VHDL)

C/C++ for automation

Python scripting

Static Timing Analysis (STA)

Education

Master's degree in Electrical & Computer Engineering

Job description

Apple in Cupertino, California is seeking an experienced ASIC Timing Engineer to drive timing closure for high-end mobile SoCs. You will develop timing constraints and coverage analysis, and create scripts for critical path analysis, working across RTL, synthesis, and physical implementation.

The role emphasizes collaboration with multiple teams to resolve timing issues and maintain robust timing methodologies and flows throughout the project lifecycle.