IC Package Design Engineer: 2.5D/3D Architect & Automation

AnySilicon; Palo Alto (CA); On-site; USD 140,000 - 200,000; Full time

Job summary

Anysilicon in Palo Alto, CA seeks an IC Package Design Engineer to drive advanced packaging for high‑performance ICs. You will lead flip-chip BGA and 2.5D/3D stackups, and co-design die/package/PCB with cross‑functional teams.

Expect to define high‑speed interfaces, optimize PDN, and perform DRC/LVS checks. You'll automate layout flows with Python/Tcl and work with OSATs and vendors from concept to production.

Qualifications

• 3 years of experience in semiconductor package and substrate layout design; 5 years preferred.
• Proficiency in electromagnetics, impedance control, and thermal management.
• Experience with heterogeneous integration and OSATs preferred.

Responsibilities

• Design advanced IC packaging solutions such as flip-chip BGA and 2.5D/3D architectures.
• Collaborate on die/package/PCB co-design and floor planning.
• Define and route high-speed interfaces and design robust Power Delivery Networks.
• Manage complex package layouts using industry-standard EDA tools.
• Conduct DRC and LVS checks.
• Generate manufacturing collateral for tapeout and manufacturing release.
• Work with SI/PI, thermal, and mechanical teams for design convergence.
• Interface with vendors and OSAT partners for design feasibility and material selection.
• Assist in lab bring-up, debugging, and silicon validation.
• Develop scripting tools to automate layout flows and enhance efficiency.
• Explore AI/ML methodologies for productivity improvements.

Skills

Semiconductor packaging

Substrate layout design

Scripting (Python Tcl Perl MATLAB)

High-speed interconnects

DFM/DFT principles

Education

B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, Mechanical Engineering, or related field

Tools

Cadence Allegro APD/SiP

Synopsys 3DICC

Job description

Anysilicon in Palo Alto, CA seeks an IC Package Design Engineer to drive advanced packaging for high‑performance ICs. You will lead flip-chip BGA and 2.5D/3D stackups, and co-design die/package/PCB with cross‑functional teams.

Expect to define high‑speed interfaces, optimize PDN, and perform DRC/LVS checks. You'll automate layout flows with Python/Tcl and work with OSATs and vendors from concept to production.