Senior IC Packaging Engineer | Chiplet & SiP Expert

Axiado Corporation; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Axiado Corporation in the Silicon Valley area seeks a Senior IC Packaging Engineer to lead advanced IC and SiP packaging, driving architectures from 2D to 2.5D fan-out and chiplet integration. You will partner with foundries and OSATs to shape production ramp and long-term packaging strategy.

You will guide design and layout under high-speed interfaces, influence roadmaps, and establish scalable packaging methods across complex programs.

Qualifications

• Minimum 10+ years of IC packaging experience for SoCs, ASICs, or memory products.
• Hands-on Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe).
• Strong understanding of electrical, mechanical, thermal, and reliability trade-offs; advanced packaging materials and substrate technologies; DFM and yield optimization.
• Demonstrated ability to operate autonomously and execute in a startup environment.

Responsibilities

• Serve as technical authority for IC and SiP packaging across multiple products and programs.
• Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
• Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
• Perform and guide hands-on package design and physical layout for high-speed interfaces (PCIe/SerDes, CXL, LPDDR5).
• Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
• Drive SI/PI, thermal, mechanical, and reliability trade-offs at system and package levels.
• Lead external engagement with OSATs, foundries, and suppliers for development and ramp.
• Influence product roadmap, risk management, and investment decisions through technical insight.
• Establish scalable design methodologies and reusable packaging flows.

Skills

IC packaging

SiP packaging

Chiplet architectures

UCIe

High-speed SerDes

DFM & yield

Cross-functional leadership

Education

BSEE or MSEE

PhD a plus

Tools

Cadence Allegro APD

HFSS

SIwave

Ansys Designer

Job description

Axiado Corporation in the Silicon Valley area seeks a Senior IC Packaging Engineer to lead advanced IC and SiP packaging, driving architectures from 2D to 2.5D fan-out and chiplet integration. You will partner with foundries and OSATs to shape production ramp and long-term packaging strategy.

You will guide design and layout under high-speed interfaces, influence roadmaps, and establish scalable packaging methods across complex programs.