Senior IC Package Layout Engineer (2.5D/3D-IC)

Annapurna Labs; San Diego (CA); On-site; USD 154,000 - 215,000; Full time

Job summary

Annapurna Labs (U.S.) Inc. is seeking a Package Layout Design Engineer to join our hardware team.

You will drive the physical design of advanced IC packages for ML and data-center ASICs, from floor planning through tape-out, working with SI/PI, thermal, and manufacturing teams to deliver production-ready designs. The ideal candidate has a BS in EE or related field, 5+ years in IC package layout, and hands-on experience with Cadence APD/SiP, Synopsys IC Packaging, and Mentor Xpedition.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 5+ years IC package layout experience.
• Experience from concept to tape-out for multi-layer substrates or interposers.
• Hands-on with Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition.
• Understanding of 2.5D/3D-IC, fan-out WLP, RDL, TSV, or similar.
• Strong communication across design, SI/PI, and manufacturing teams.

Responsibilities

• Execute package layout tasks across the design cycle: floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape-out release.
• Implement physical designs for 2.5D/3D-IC, fan-out WLP, and silicon bridge interconnects.
• Support floorplan development including die placement and power/ground distribution.
• Perform RDL and substrate routing for high-density interconnects.
• Coordinate with ASIC physical design teams to optimize die-package interface.
• Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels.
• Maintain package stack-up definitions with SI/PI and materials teams.
• Run physical verification checks (DRC, connectivity) and help design closure.
• Follow design rules and work with OSAT partners for DFM.

Skills

Package layout

IC packaging tools

2.5D/3D-IC

Cross-functional collaboration

DFM & design rules

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree in Electrical/Communications Engineering

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs (U.S.) Inc. is seeking a Package Layout Design Engineer to join our hardware team.

You will drive the physical design of advanced IC packages for ML and data-center ASICs, from floor planning through tape-out, working with SI/PI, thermal, and manufacturing teams to deliver production-ready designs. The ideal candidate has a BS in EE or related field, 5+ years in IC package layout, and hands-on experience with Cadence APD/SiP, Synopsys IC Packaging, and Mentor Xpedition.