Senior IC Package Layout Engineer (2.5D/3D)

Amazon Inc.; Tempe, Cupertino, Austin (AZ, CA, TX); Vor Ort; USD 154.000 - 215.000; Vollzeit

Zusammenfassung

Annapurna Labs, within AWS, seeks a Package Layout Design Engineer to advance the physical design of IC packages for next‑gen ML and data center ASICs in Tempe, AZ. You will drive layout from floor planning through tape-out, collaborating with SI/PI, thermal, and manufacturing teams to ensure performance and reliability.

Responsibilities include RDL/substrate routing, die-to-package interface optimization, design rule adherence, and DFM compliance with OSAT partners.

Qualifikationen

• Bachelor's degree in Electrical Engineering or related field.
• Experience debugging architecture, algorithms, and performance.
• Experience verifying logic from IP to SoCs to full system testing.
• 5+ years in IC package layout and physical design.
• Experience taking package designs from concept through tape-out on multi-layer substrates.

Aufgaben

• Execute package layout tasks from floor planning to tape-out release.
• Implement 2.5D/3D-IC packaging architectures, including advanced technologies.
• Support floorplan development including die placement and power distribution.
• Perform RDL and substrate routing for high-density interconnects.
• Coordinate with ASIC physical design teams to optimize die-package interface.
• Contribute to cross-level layout co-optimization across multiple design levels.
• Assist in maintaining package stack-up definitions with SI/PI teams.
• Run physical verification checks (DRC, connectivity) and support design closure.
• Follow design rules with OSAT partners to ensure DFM compliance.
• Collaborate with SI/PI for impedance, PDN layout, and shielding constraints.

Kenntnisse

Package layout

IC packaging

Design verification

Cadence APD/SiP

Cross-team communication

Ausbildung

Bachelor's degree in Electrical Engineering

Master's degree (preferred)

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Jobbeschreibung

Annapurna Labs, within AWS, seeks a Package Layout Design Engineer to advance the physical design of IC packages for next‑gen ML and data center ASICs in Tempe, AZ. You will drive layout from floor planning through tape-out, collaborating with SI/PI, thermal, and manufacturing teams to ensure performance and reliability.

Responsibilities include RDL/substrate routing, die-to-package interface optimization, design rule adherence, and DFM compliance with OSAT partners.