Hybrid VLSI Design Verification Intern (MS)

Hewlett Packard Enterprise Company; Fort Collins (CO); Hybrid; USD 55,000 - 63,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Hewlett Packard Enterprise Company in Colorado is seeking a VLSI Design Verification Masters Level Intern. The role is hybrid, requiring on-site work about 2 days per week, with hands-on work on Slingshot ASIC verification and AI-assisted tooling.

You will learn industry-standard SystemVerilog/UVM and collaborate with designers and architects on high-performance interconnect projects. Ideal candidates are pursuing a Master’s degree in relevant fields, with coursework in digital design,

Qualifications

• Pursuing a Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Coursework in digital design and computer architecture is expected.
• Experience with object-oriented programming.
• Strong analytical and problem-solving skills.
• Clear written and verbal communication skills.
• Willingness to ask questions and participate in technical discussions.

Responsibilities

• Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers.
• Write constrained-random tests.
• Develop and analyze functional coverage to identify verification gaps.
• Debug regression failures and help identify, log, and resolve logic bugs.
• Work directly with ASIC designers and architects.
• Use scripting, automation, and AI-assisted tools to improve the verification process.

Skills

Object-oriented programming

Analytical thinking

Communication skills

Education

Master's degree (pursuing) in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Verilog

SystemVerilog

VHDL

Job description

Hewlett Packard Enterprise Company in Colorado is seeking a VLSI Design Verification Masters Level Intern. The role is hybrid, requiring on-site work about 2 days per week, with hands-on work on Slingshot ASIC verification and AI-assisted tooling.

You will learn industry-standard SystemVerilog/UVM and collaborate with designers and architects on high-performance interconnect projects. Ideal candidates are pursuing a Master’s degree in relevant fields, with coursework in digital design,