Hybrid VLSI Design Verification Intern (MS)

Hewlett Packard Enterprise; Fort Collins (CO); Hybrid; USD 114,616,000 - 132,029,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a VLSI Design Verification Masters Level Intern in a hybrid role requiring two days per week in an HPE office in Colorado. You will collaborate with architects and verification engineers on a Slingshot switch/NIC ASIC verification project, learning SystemVerilog, UVM, and AI-assisted workflows.

The role targets students pursuing a Master’s degree in EE/CE/CS with coursework in digital design and architecture, plus programming experience in Python and

Qualifications

• Pursuing a Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Coursework in digital design and computer architecture.
• Experience with object-oriented programming.
• Strong analytical and problem-solving skills.
• Clear written and verbal communication skills.
• Willingness to ask questions, explain your reasoning, and participate in technical discussions.

Responsibilities

• Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers.
• Write constrained-random tests.
• Develop and analyze functional coverage to identify verification gaps.
• Debug regression failures and help identify, log, and resolve logic bugs.
• Work directly with ASIC designers and architects.
• Use scripting, automation, and AI-assisted tools to improve the verification process.

Skills

Strong analytical skills

Clear written and verbal communication

Object-oriented programming

Python

Perl/Tcl scripting

Linux development

Education

Master's degree pursuit in EE/CE/CS

Digital design coursework

Computer architecture coursework

Tools

Verilog/SystemVerilog/VHDL

Job description

Hewlett Packard Enterprise is seeking a VLSI Design Verification Masters Level Intern in a hybrid role requiring two days per week in an HPE office in Colorado. You will collaborate with architects and verification engineers on a Slingshot switch/NIC ASIC verification project, learning SystemVerilog, UVM, and AI-assisted workflows.

The role targets students pursuing a Master’s degree in EE/CE/CS with coursework in digital design and architecture, plus programming experience in Python and