Hybrid VLSI Verification Intern — SystemVerilog & UVM

Hewlett Packard Enterprise Company

Chippewa Falls (WI)

Hybrid

USD 48,000 - 56,000

Full time

6 days ago
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Job summary

Hewlett Packard Enterprise Company in Wisconsin is offering a VLSI Design Verification Internship. You will work with experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for Slingshot, learning SystemVerilog and UVM verification techniques.

The internship targets students pursuing a bachelor's or master's degree in EE/CE/CS, with experience in object-oriented programming, strong problem-solving, and good communication.

Qualifications

  • Pursuing a bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Coursework in digital design and computer architecture
  • Experience with object-oriented programming
  • Strong analytical and problem-solving skills
  • Clear written and verbal communication skills
  • Willingness to ask questions, explain your reasoning, and participate in technical discussions

Responsibilities

  • Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers
  • Write constrained-random tests
  • Develop and analyze functional coverage to identify verification gaps
  • Debug regression failures and help identify, log, and resolve logic bugs
  • Work directly with ASIC designers and architects
  • Use scripting, automation, and AI-assisted tools to improve the verification process

Skills

SystemVerilog/UVM testbench
OO programming
Analytical problem solving
Written & verbal communication

Education

Bachelor's or Master's in EE/CE/CS

Tools

Verilog/SystemVerilog/VHDL
Python
Linux

Job description

Hewlett Packard Enterprise Company in Wisconsin is offering a VLSI Design Verification Internship. You will work with experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for Slingshot, learning SystemVerilog and UVM verification techniques.

The internship targets students pursuing a bachelor's or master's degree in EE/CE/CS, with experience in object-oriented programming, strong problem-solving, and good communication.

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