Hybrid ASIC Design & Verification Intern

Hewlett Packard Enterprise Company; Roseville (CA); Híbrido; USD 48.000 - 56.000; A tiempo parcial

Descripción de la vacante

Hewlett Packard Enterprise seeks an ASIC Verification/Design Engineering Intern to join the Aruba ASIC team. The role is hybrid, with an expectation to work on average 2 days per week from an HPE office and contribute to next‑gen networking chips.

You will learn from senior ASIC/VLSI engineers with projects spanning RTL/Physical Design, verification, and tool development during the summer. Strong fundamentals and eagerness to learn are essential.

Formación

• Enrolled in a 4-year engineering/CS/EE degree program.
• At least 3rd year of engineering completed by 2027/2028.
• Interest in ASIC design and verification in a team environment.

Responsabilidades

• RTL/Physical Design support and development tasks.
• Pre-Silicon verification and post-silicon verification activities.
• Formal verification work and script/tool development.
• Schedule breakdowns, documentation, and other duties as needed.
• Collaborate with senior ASIC/VLSI engineers on project goals.

Conocimientos

Python

PERL

TCL

C/C++

Hardware design

AI tools

Excellent communication

Time management

Team collaboration

Educación

4-year University/College engineering or CS program, in progress

3rd year completed by Dec 2027 or May 2028

Herramientas

Python

PERL

TCL

Verilog

C/C++

AI tools

Descripción del empleo

Hewlett Packard Enterprise seeks an ASIC Verification/Design Engineering Intern to join the Aruba ASIC team. The role is hybrid, with an expectation to work on average 2 days per week from an HPE office and contribute to next‑gen networking chips.

You will learn from senior ASIC/VLSI engineers with projects spanning RTL/Physical Design, verification, and tool development during the summer. Strong fundamentals and eagerness to learn are essential.