Hybrid VLSI Logic Design Intern

Hewlett Packard Enterprise Company; Chippewa Falls (WI); Hybrid; USD 48,000 - 56,000; Part time

Job summary

Hewlett Packard Enterprise invites applications for a VLSI Logic Design Intern in Wisconsin. The role is designed as hybrid with an on-site requirement averaging 2 days per week at an HPE office.

You will contribute to RTL design, verification, and scripting to improve design processes. We're looking for students pursuing a Bachelor's or Master's in Electrical or Computer Engineering with SystemVerilog experience and strong English communication.

Qualifications

• Working toward a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent.
• Self-driven with a positive, can-do attitude, and detail-oriented.
• Experience with System Verilog for synthesis (ASIC or FPGA).
• Proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience in executive written and verbal communication skills; mastery in English.
• Ability to work with cross functional teams (DV/Arch/Design/FW).

Responsibilities

• Assist with VLSI / RTL design using System Verilog.
• Assist with creating System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
• Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Skills

SystemVerilog

Cross-functional teamwork

Digital design

Verilog/SystemVerilog verification

Python scripting

English communication

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

UVM

SystemVerilog tooling

Job description

Hewlett Packard Enterprise invites applications for a VLSI Logic Design Intern in Wisconsin. The role is designed as hybrid with an on-site requirement averaging 2 days per week at an HPE office.

You will contribute to RTL design, verification, and scripting to improve design processes. We're looking for students pursuing a Bachelor's or Master's in Electrical or Computer Engineering with SystemVerilog experience and strong English communication.