Hybrid ASIC Verification/Design Intern (RTL, Python)

Hewlett Packard Enterprise; Roseville (CA); Hybrid; USD 48,000 - 56,000; Part time

Benefits offered by this job

Health & Wellbeing

Personal & Professional Development

Unconditional Inclusion

Job summary

Hewlett Packard Enterprise invites you to join our ASIC/Verilog team in California as a Verification/Design Engineering Intern. You will contribute to RTL/Physical Design and both pre- and post-silicon verification under senior engineers, while developing scripts and tools.

This hybrid role requires about two days per week on-site in Roseville, CA, with an expected hourly salary range of $35–$41. We value initiative, strong communication, and eagerness to learn about high‑tech networking chips.

Qualifications

• Must be currently enrolled in a 4-year University/College pursuing a degree in Computer Engineering, Computer Science, Electrical Engineering or equivalent.
• At least 3rd Year of engineering courses completed (December 2027 or May 2028 degree completion).
• Experience with scripting languages (Python, PERL, TCL or equivalent)
• Experience with hardware design
• Experience with software programming languages (C; C++)
• Experience with Verilog
• Strong interest in high-tech and a passion for learning
• Excellent communication and interpersonal skills
• Strong problem-solving and analytical skills
• Time management skills and working with strict deadlines
• A collaborative, solution-focused mindset and overall sense of urgency
• Experience with AI tools.

Responsibilities

• RTL/Physical Design tasks for ASIC development.
• Pre-Silicon verification activities.
• Post-silicon verification activities.
• Formal Verification work.
• Script & Tool development for automation.
• Schedule breakdowns and documentation generation.

Skills

Python

PERL

TCL

Verilog

C/C++

Hardware design

AI tools

Communication

Education

Bachelor's degree in Computer Engineering/CS/EE or equivalent

At least 3rd Year engineering courses completed

Tools

Verilog tools

Scripting tools

Job description

Hewlett Packard Enterprise invites you to join our ASIC/Verilog team in California as a Verification/Design Engineering Intern. You will contribute to RTL/Physical Design and both pre- and post-silicon verification under senior engineers, while developing scripts and tools.

This hybrid role requires about two days per week on-site in Roseville, CA, with an expected hourly salary range of $35–$41. We value initiative, strong communication, and eagerness to learn about high‑tech networking chips.