Hybrid VLSI Logic Design Intern (SystemVerilog)

Hewlett Packard Enterprise Company; Fort Collins (CO); Hybride; USD 48 000 - 56 000; Plein temps

Avantages offerts par ce poste

Hybrid work environment

Inclusive culture

Résumé du poste

Hewlett Packard Enterprise offers a VLSI Logic Design Intern position in Colorado with a hybrid work arrangement requiring about 2 days per week in an HPE office. The role focuses on VLSI/RTL design using SystemVerilog, asserting properties with SVAs, and applying Formal Verification to ensure correctness.

The intern will also develop coverage metrics, write scripts in Python/TCL/Perl, and collaborate with DV/Arch/Design/FW teams.

Qualifications

• Pursuing a Bachelor's or Master's in Electrical or Computer Engineering or equivalent.
• Self-driven with a positive, can-do attitude and detail-oriented.
• Experience with SystemVerilog for synthesis (ASIC or FPGA).
• Proficiency in EE fundamentals, VLSI, digital logic, and computer architecture.
• Strong written and verbal English communication.
• Ability to work with cross-functional teams (DV/Arch/Design/FW).

Responsabilités

• Assist with VLSI / RTL design using System Verilog.
• Assist with creating System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
• Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Connaissances

SystemVerilog

Python

TCL

Perl

Verbal English

Cross-functional teamwork

Formation

Bachelor's or Master's in Electrical or Computer Engineering

Outils

UVM

SystemVerilog (synthesis)

Description du poste

Hewlett Packard Enterprise offers a VLSI Logic Design Intern position in Colorado with a hybrid work arrangement requiring about 2 days per week in an HPE office. The role focuses on VLSI/RTL design using SystemVerilog, asserting properties with SVAs, and applying Formal Verification to ensure correctness.

The intern will also develop coverage metrics, write scripts in Python/TCL/Perl, and collaborate with DV/Arch/Design/FW teams.