Hybrid VLSI Logic Design Intern

Hewlett Packard Enterprise; Chippewa Falls (WI); Hybrid; USD 48,000 - 56,000; Part time

Job summary

Hewlett Packard Enterprise invites students pursuing degrees in Electrical or Computer Engineering to join the Cray Slingshot team as a tooling and verification-focused intern. You will work on VLSI/RTL design using SystemVerilog and contribute to SVAs, formal verification, and coverage analysis while building automation scripts in Python, TCL, and Perl.

Ideal candidates are self-driven, detail-oriented, and capable of communicating effectively in English within cross-functional DV/Arch/Design

Qualifications

• Working toward a Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering or equivalent.
• Strong communication skills in English and ability to work with cross‑functional teams.
• Experience with SystemVerilog for synthesis (ASIC or FPGA).

Responsibilities

• Assist with VLSI / RTL design using System Verilog.
• Assist with creating System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
• Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Skills

SystemVerilog

English communication

Cross-functional teamwork

DV/Arch/Design collaboration

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Python

TCL

Perl

C/C++

Job description

Hewlett Packard Enterprise invites students pursuing degrees in Electrical or Computer Engineering to join the Cray Slingshot team as a tooling and verification-focused intern. You will work on VLSI/RTL design using SystemVerilog and contribute to SVAs, formal verification, and coverage analysis while building automation scripts in Python, TCL, and Perl.

Ideal candidates are self-driven, detail-oriented, and capable of communicating effectively in English within cross-functional DV/Arch/Design