Lead Design Verification Manager: Scale SoC Validation

Hobbsnews; Sunnyvale (CA); On-site; USD 174,000 - 352,500; Full time

Job summary

Hewlett Packard Enterprise is seeking a Design Verification Manager to lead a world-class silicon verification team, guiding verification strategies and testbench architecture for high-performance SoCs. You will pair architectural insight with hands-on verification, drive cross-functional collaboration, and ensure timely tape-outs across multiple projects in California.

The role requires 10+ years in pre-silicon verification and 5+ years in leadership, with expertise in SystemVerilog, UVM, and

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Science, Computer Engineering, or a closely related technical field.
• 10+ years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification.
• 5+ years of dedicated engineering management or formal team leadership experience.
• Proven mastery building scalable UVM-compliant testbenches from scratch.

Responsibilities

• Lead and mentor a team of high-performing design verification engineers.
• Define global verification strategies, infrastructure, and testbench architecture for complex SoCs.
• Allocate resources across multiple parallel chip/block schedules.
• Drive standard-setting verification methodology and automated flows across teams.
• Collaborate with Architecture, RTL Design, Physical Design and Post-Silicon validation.

Skills

SystemVerilog

UVM

Formal verification

Emulation

Palladium

Zebu

Veloce

Education

Bachelor’s degree

Master’s degree

PhD

Tools

Palladium

Zebu

Veloce

Job description

Hewlett Packard Enterprise is seeking a Design Verification Manager to lead a world-class silicon verification team, guiding verification strategies and testbench architecture for high-performance SoCs. You will pair architectural insight with hands-on verification, drive cross-functional collaboration, and ensure timely tape-outs across multiple projects in California.

The role requires 10+ years in pre-silicon verification and 5+ years in leadership, with expertise in SystemVerilog, UVM, and