Hybrid ASIC Verification Intern - Summer Project

Hewlett Packard Enterprise Company; Roseville (CA); Hybrid; USD 30,000 - 44,000; Full time

Job summary

Hewlett Packard Enterprise Company invites applications for an ASIC Post-Si Verification Engineering Intern in Roseville, CA. You will collaborate with the HPE Aruba ASIC development team on next-generation networking chips, with a summer project contributing to current or future ASICs.

The role offers hands-on learning across RTL/Physical Design, Pre- and Post-Silicon verification, scripting and tool development, and opportunities to gain real-world experience in a global tech leader committed

Qualifications

• Pursuing a technical degree in a related field.
• Completed at least 3rd year of engineering coursework.
• Knowledge of Verilog/SystemVerilog and scripting languages.
• Strong communication and teamwork abilities.

Responsibilities

• Collaborate with the ASIC development team on next-generation products.
• Complete a summer project aligned with ASIC development activities.
• Assist RTL/Physical Design, Pre- and Post-Silicon verification, and scripting/tool development.

Skills

Verilog/SystemVerilog

Python

C/C++

Hardware design

Communication skills

Problem-solving

Teamwork

Education

Bachelor's or Master's degree in Computer Engineering/CS/EE

Job description

Hewlett Packard Enterprise Company invites applications for an ASIC Post-Si Verification Engineering Intern in Roseville, CA. You will collaborate with the HPE Aruba ASIC development team on next-generation networking chips, with a summer project contributing to current or future ASICs.

The role offers hands-on learning across RTL/Physical Design, Pre- and Post-Silicon verification, scripting and tool development, and opportunities to gain real-world experience in a global tech leader committed