Hybrid Senior ASIC Engineering Manager — High-Speed Design

Anysilicon; Sunnyvale (CA); Sur place; USD 180 000 - 240 000; Plein temps

Résumé du poste

Hewlett Packard Enterprise (HPE) seeks a Senior Manager for its ASIC Engineering team in a hybrid role requiring in-office work two days a week in Sunnyvale, CA. You will lead a design and verification group for high-speed ASICs used in networking products, guiding from specification to tapeout while mentoring engineers.

The role demands 10+ years in ASIC and proven leadership, with strong Verilog/SystemC/C/C++ and scripting skills, and the ability to manage multiple complex projects

Qualifications

• BS/MS in Electrical Engineering or equivalent field.
• 10+ years of ASIC experience, including engineering management.
• Strong skills in Verilog, SystemC, C/C++, and scripting languages.
• Proven leadership and communication abilities.
• Experience managing multiple ASIC projects from start to finish.

Responsabilités

• Manage design and verification team for complex high-speed ASICs.
• Lead a team of engineers from specification to tapeout.
• Create and maintain project schedules.
• Collaborate with logic designers and software developers.
• Mentor junior engineers in verification strategies.

Connaissances

ASIC design

Verification strategies

Leadership

Project management

Formation

BS/MS in Electrical Engineering or equivalent

Outils

Verilog

SystemC

C/C++

Scripting languages

Description du poste

Hewlett Packard Enterprise (HPE) seeks a Senior Manager for its ASIC Engineering team in a hybrid role requiring in-office work two days a week in Sunnyvale, CA. You will lead a design and verification group for high-speed ASICs used in networking products, guiding from specification to tapeout while mentoring engineers.

The role demands 10+ years in ASIC and proven leadership, with strong Verilog/SystemC/C/C++ and scripting skills, and the ability to manage multiple complex projects