Hybrid Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise Company; Fort Collins (CO); Hybrid; USD 147,000 - 279,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer in Colorado for a hybrid role requiring on-site 2 days per week. You will contribute to synthesis, timing, and signoff for complex ASICs, collaborating with cross-functional teams across architecture, DFT, and signal integrity.

The role emphasizes physical-design-aware methodologies and scalable flows. Required 6–10 years in ASIC/VLSI with expertise in timing closure, STA, and EDA tools; strong scripting in Python or

Qualifications

• Typically 6–10 years in ASIC/VLSI design and timing closure.
• Strong grasp of digital logic, circuit design, and architecture.

Responsibilities

• Perform static timing analysis for hierarchical designs.
• Create and maintain timing constraints and budgets.
• Drive timing closure for partitioned and full-chip designs.
• Develop flow automation for synthesis and verification.
• Collaborate with cross-functional teams on physical design.

Skills

Static timing

Timing constraints

Synthesis

Formal verification

Floorplanning

Partitioning

ECO implementation

Python scripting

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence Genus

CADENCE LEC

RTL Compiler

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer in Colorado for a hybrid role requiring on-site 2 days per week. You will contribute to synthesis, timing, and signoff for complex ASICs, collaborating with cross-functional teams across architecture, DFT, and signal integrity.

The role emphasizes physical-design-aware methodologies and scalable flows. Required 6–10 years in ASIC/VLSI with expertise in timing closure, STA, and EDA tools; strong scripting in Python or