Hybrid Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise Development LP; Fort Collins (CO); Hybrid; USD 147,000 - 279,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer in Colorado to design and implement high‑performance ICs. You will collaborate with ASIC design, physical implementation, DFT, signal integrity, and architecture teams to enable physically aware designs and scalable methodologies.

You will drive timing closure, create timing budgets, and develop automation for synthesis, timing analysis, and signoff.

Qualifications

• Degree in a technical field (EE/CE/CS/Microelectronics).
• Typically 6–10 years in ASIC/VLSI or semiconductor design with physical design timing closure experience.
• Strong knowledge of digital logic, circuit design, and ASIC physical design.

Responsibilities

• Perform static timing analysis for hierarchical designs at partition and full-chip levels.
• Create and maintain timing constraints and budgets for design and process requirements.
• Drive timing closure for partition-level and full-chip designs.
• Analyze timing reports, identify critical paths, and implement fixes for performance/ power/area goals.
• Perform synthesis, netlist quality checks, and formal verification.
• Support chip partitioning, floorplanning, and physical design implementation.
• Create and manage ECOs and develop flow automation for synthesis and timing analysis.
• Mentor engineers and promote best practices across the design organization.

Skills

Static timing analysis

Timing constraints

Scripting (Python, Perl, Tcl)

Education

Bachelor's or Master's in Electrical/Computer Engineering, Computer Science, or Microelectronics

Tools

Synopsys Fusion Compiler

Design Compiler

PrimeTime

Formality

Cadence RTL Compiler

Job description

Hewlett Packard Enterprise is seeking a Senior ASIC Physical Design Engineer in Colorado to design and implement high‑performance ICs. You will collaborate with ASIC design, physical implementation, DFT, signal integrity, and architecture teams to enable physically aware designs and scalable methodologies.

You will drive timing closure, create timing budgets, and develop automation for synthesis, timing analysis, and signoff.