Senior Manager, ASIC Engineering

Anysilicon; Sunnyvale (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) seeks a Senior Manager for its ASIC Engineering team in a hybrid role requiring in-office work two days a week in Sunnyvale, CA. You will lead a design and verification group for high-speed ASICs used in networking products, guiding from specification to tapeout while mentoring engineers.

The role demands 10+ years in ASIC and proven leadership, with strong Verilog/SystemC/C/C++ and scripting skills, and the ability to manage multiple complex projects

Qualifications

• BS/MS in Electrical Engineering or equivalent field.
• 10+ years of ASIC experience, including engineering management.
• Strong skills in Verilog, SystemC, C/C++, and scripting languages.
• Proven leadership and communication abilities.
• Experience managing multiple ASIC projects from start to finish.

Responsibilities

• Manage design and verification team for complex high-speed ASICs.
• Lead a team of engineers from specification to tapeout.
• Create and maintain project schedules.
• Collaborate with logic designers and software developers.
• Mentor junior engineers in verification strategies.

Skills

ASIC design

Verification strategies

Leadership

Project management

Education

BS/MS in Electrical Engineering or equivalent

Tools

Verilog

SystemC

C/C++

Scripting languages

Job description

Job Description:

Hewlett Packard Enterprise (HPE) is seeking a Senior Manager for its ASIC Engineering team, focusing on the design and verification of high-speed ASICs for next-generation networking products. This hybrid role requires in-office work two days a week and offers a dynamic environment that combines the agility of a startup with the resources of a large corporation.

Responsibilities:

• Manage design and verification team for complex high-speed ASICs.
• Lead a team of engineers from specification to tapeout.
• Create and maintain project schedules.
• Collaborate with logic designers and software developers.
• Mentor junior engineers in verification strategies.

Qualifications:

• BS/MS in Electrical Engineering or equivalent field.
• 10+ years of ASIC experience, including engineering management.
• Strong skills in Verilog, SystemC, C/C++, and scripting languages.
• Proven leadership and communication abilities.
• Experience managing multiple ASIC projects from start to finish.

Skills:

• Expertise in ASIC design and verification.
• Strong programming skills in Verilog, SystemC, or C/C++.
• Ability to mentor and develop engineering talent.
• Excellent project management and scheduling skills.

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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