Hybrid ASIC Verification Engineer – UVM/SoC Expert

Hewlett Packard Enterprise

Sunnyvale (CA)

Hybrid

USD 124,000 - 251,000

Full time

4 hours ago
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Job summary

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team. The role requires working in a hybrid model with about two days per week in an HPE office.

You will own verification efforts for block or subsystem levels, develop advanced UVM environments, and collaborate across teams to deliver high-quality ASIC/SoC products. Strong SystemVerilog and UVM expertise is essential.

Qualifications

  • 7+ years of ASIC/SoC verification experience with ownership from test plan to coverage closure.
  • Strong expertise in SystemVerilog and UVM with environment development from scratch.
  • Familiarity with randomization, constraints, functional coverage, and SVA assertions.

Responsibilities

  • Own and drive block-level or subsystem verification efforts from test plans to coverage closure.
  • Develop, enhance, and maintain advanced UVM verification environments including agents, sequences, scoreboards, and register models.
  • Perform constrained random testing and debug complex SoC designs to ensure functional coverage and assertions goals.
  • Analyze simulation results with industry tools and debug waveforms to validate functionality.
  • Collaborate with cross-functional teams to deliver high-quality ASIC/SoC deliverables.

Skills

SystemVerilog
UVM
Test planning
Simulation tools
SoC verification

Tools

Cadence Xcelium
Synopsys VCS
Mentor Questa

Job description

Hewlett Packard Enterprise in Sunnyvale, CA is seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team. The role requires working in a hybrid model with about two days per week in an HPE office.

You will own verification efforts for block or subsystem levels, develop advanced UVM environments, and collaborate across teams to deliver high-quality ASIC/SoC products. Strong SystemVerilog and UVM expertise is essential.

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