ASIC Design Engineer II – Networking ASICs

Anysilicon; Sunnyvale (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Hewlett Packard Enterprise (HPE) seeks an ASIC Design Engineer 2 to join the Juniper Silicon group in Sunnyvale, CA. Onsite role focusing on advanced networking chips and collaboration with cross-functional teams.

Responsibilities include developing micro-architecture specs, RTL coding, and ensuring timing and verification using modern EDA tools. Strong foundation in digital design and system Verilog is required.

Qualifications

• BS in Electrical Engineering required.
• Master's degree strongly desired.
• Coursework in digital logic essential.
• Strong analytical and problem-solving skills.

Responsibilities

• Develop micro-architecture specs from functional specs under guidance.
• Perform RTL coding in SystemVerilog for projects.
• Create functional coverage and SVA; training provided if needed.
• Collaborate with PD to fix RTL timing to meet targets.
• Debug verification issues using advanced EDA tools.

Skills

Verilog/SystemVerilog

RTL coding

SVA

Python/Perl

Analytical skills

Communication skills

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

SystemVerilog simulators

EDA tools

Git

Job description

Hewlett Packard Enterprise (HPE) seeks an ASIC Design Engineer 2 to join the Juniper Silicon group in Sunnyvale, CA. Onsite role focusing on advanced networking chips and collaboration with cross-functional teams.

Responsibilities include developing micro-architecture specs, RTL coding, and ensuring timing and verification using modern EDA tools. Strong foundation in digital design and system Verilog is required.