Hybrid ASIC Packaging SI/PI Engineer – 2.5D/CoWoS

Cisco Systems, Inc; San Jose (CA); On-site; USD 126,000 - 177,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Bonus program

Job summary

Cisco Silicon One seeks a qualified Signal and Power Integrity Engineer to help define, design, and verify ASIC packaging for high-volume Cisco platforms. You will analyze SI/PI, perform pre- and post-layout validation, and collaborate with layout teams to meet stringent power, performance, and area targets.

The role requires hands-on measurement planning, lab characterization, and strong cross-functional collaboration to ensure reliable, high-speed interconnects across interposer, substrate,

Qualifications

• Experience with high-speed design principles, including 56G PAM4 SerDes architectures and BER prediction.
• Experience in pre- and post-layout SI/PI analysis with industry-standard tools and lab validation.
• Experience with lab measurements (VNA, TDR) and correlation to simulations.
• Familiarity with design flows for ASIC packaging and post-layout extraction.
• Collaborative work with layout and system teams to optimize SI/PI.

Responsibilities

• Develop and verify ASIC packaging for high-volume release.
• Create design rules for ultra-high-speed signaling to meet power/performance/area goals.
• Analyze substrate SI/PI and provide feedback to the layout team.
• Document and develop ASIC packages including post-layout extraction and reporting.
• Collaborate with system partners to resolve SI/PI issues across interposer, substrate, and PCB.

Skills

High-Speed Design

SI/PI Simulation

VNA Measurements

Lab Debugging

Cadence Sigrity

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

VNA/TDR equipment

Job description

Cisco Silicon One seeks a qualified Signal and Power Integrity Engineer to help define, design, and verify ASIC packaging for high-volume Cisco platforms. You will analyze SI/PI, perform pre- and post-layout validation, and collaborate with layout teams to meet stringent power, performance, and area targets.

The role requires hands-on measurement planning, lab characterization, and strong cross-functional collaboration to ensure reliable, high-speed interconnects across interposer, substrate,