High-Speed ASIC Packaging & SI/PI Engineer (2.5D)

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Job summary

Cisco Silicon One in San Jose is seeking an experienced Electrical Engineer to design and validate ultra-high-speed signaling for next-generation ASICs. You will analyze substrate SI/PI, collaborate with layout and system teams, and contribute to post-layout extraction and reporting.

The role requires strong background in high-speed design theory, PAM4 SerDes, and SPICE-level circuit analysis, with experience in Cadence Sigrity, Ansys HFSS, and Keysight ADS.

Qualifications

• Bachelor's degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience; or Master's with 2+ years; or PhD with 0+ years.
• High-Speed Design & Theory: 56G PAM4 SerDes architectures, channel modeling, BER prediction.
• SI/PI Simulation Proficiency: pre- and post-layout SI/PI simulations with Cadence Sigrity, Ansys HFSS, Keysight ADS.
• Layout Review & Physical Validation: detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows.
• Circuit Analysis: SPICE-based circuit analysis and modeling.

Responsibilities

• Develop, document, and implement design rules for ultra-high-speed signaling.
• Analyze substrate SI and PI and collaborate with layout teams for optimal solutions.
• Design, document, and develop ASIC packages including post-layout extraction and reporting.
• Collaborate with system partners and design leads to resolve complex technical issues using advanced rules.

Skills

High-speed design

SI/PI analysis

Transmission Line Theory

PAM4 SerDes

BER prediction

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Keysight ADS

Cadence APD

Ansys EM flows

Job description

Cisco Silicon One in San Jose is seeking an experienced Electrical Engineer to design and validate ultra-high-speed signaling for next-generation ASICs. You will analyze substrate SI/PI, collaborate with layout and system teams, and contribute to post-layout extraction and reporting.

The role requires strong background in high-speed design theory, PAM4 SerDes, and SPICE-level circuit analysis, with experience in Cadence Sigrity, Ansys HFSS, and Keysight ADS.