Hybrid DFT ASIC Engineer - Scan & MBIST Expert

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 155,000 - 223,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Design-for-Testability (DFT) Engineer in a hybrid role based out of San Jose, CA.

The candidate will implement, validate, and sign off DFT solutions for complex ASIC/SoC designs, collaborating with RTL, verification, physical design, and test teams to ensure high test coverage and manufacturability. You will develop and optimize DFT flows, run ATPG/MBIST tests, debug issues, and automate processes with Tcl, Python, or Perl.

Qualifications

• Bachelors + 5 years of related experience, or Master +3 years of related experience, or PhD + 0 years of related experience, or equivalent related work experience.
• Experience with ASIC DFT implementation or validation.
• Experience with industry DFT tools such as Siemens Tessent, Synopsys DFT Compiler/TestMAX, or equivalent.
• Experience with scan architecture, scan compression, ATPG, MBIST, OCC, and test-mode controls.
• Experience with stuck-at and transition fault models.
• Experience with debug DFT rule violations, scan-chain issues, ATPG coverage gaps, and pattern simulation failures.
• Scripting experience using Tcl, Python, Perl, or shell

Responsibilities

• Support DFT implementation for ASIC/SoC blocks and subsystems.
• Implement and validate scan insertion, scan compression, OCC, MBIST, boundary scan, and related DFT logic.
• Run DFT rule checks and debug scan, clock, reset, and test-mode issues.
• Generate and validate ATPG patterns for stuck-at, transition, and other required fault models.
• Analyze test coverage, pattern count, compression results, and ATPG reports.
• Debug DFT DRC violations, ATPG coverage holes, chain failures, and pattern simulation issues.
• Work with RTL and verification teams to ensure DFT requirements are correctly implemented.
• Support block-level and full-chip DFT integration activities.
• Assist with hierarchical DFT flows, pattern retargeting, and validation where applicable.
• Develop and maintain Tcl, Python, Perl, or shell scripts to automate DFT flows and reporting.
• Support silicon debug, diagnosis analysis, and yield-learning activities as needed.
• Document DFT implementation results, known issues, waivers, and signoff status.

Skills

ASIC DFT

DFT tools

scan architecture

ATPG/MBIST

Tcl/Python/Shell

Education

Bachelor's degree or higher

Tools

Siemens Tessent

Synopsys DFT Compiler/TestMAX

Job description

Cisco Systems, Inc. is seeking a Design-for-Testability (DFT) Engineer in a hybrid role based out of San Jose, CA.

The candidate will implement, validate, and sign off DFT solutions for complex ASIC/SoC designs, collaborating with RTL, verification, physical design, and test teams to ensure high test coverage and manufacturability. You will develop and optimize DFT flows, run ATPG/MBIST tests, debug issues, and automate processes with Tcl, Python, or Perl.