High Speed Serdes I.C Engineer

Cadence; San Jose (CA); On-site; USD 137,000 - 254,000; Full time

Benefits offered by this job

Paid vacation and holidays

401(k) with employer match

Employee stock purchase plan

Medical, dental and vision plans

Job summary

Cadence is seeking a Principal Analog IC Designer to lead the design and development of analog/mixed-signal IC blocks from concept through verification. The role requires deep expertise in CMOS SerDes/high-speed I/O, jitter control, and related CAD tools, with strong collaboration across teams.

Applicants should have 7+ years of CMOS SerDes experience and an MS/PhD in EE. On-site in California with competitive salary, bonus, equity, and comprehensive benefits.

Qualifications

• 7+ years of CMOS SerDes or high-speed I/O design experience.
• Knowledge of SerDes standards and electrical requirements is a plus.
• Thorough understanding of jitter and signal equalization techniques.
• Proficiency in CAD tools for circuit simulation, layout, and physical verification; Cadence experience preferred.
• Lab test experience; design experience at >10Gbps and in <28nm tech is a plus.
• MS or PhD in EE.

Responsibilities

• Design and develop analog/mixed-signal IC blocks from concept/specification to verification against customer specs.
• Work with cross-functional teams to ensure best-in-class performance and reliability.

Skills

SerDes design

Jitter techniques

Analog/mixed-signal design

High-speed I/O

Problem solving

Team collaboration

Communication skills

10Gbps design

Education

MS or PhD in EE

Tools

Cadence CAD tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.

• Candidate’s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development
• Working knowledge of a set of common SerDes standards and their electrical requirements is a plus
• Must have a thorough understanding of jitter and signal equalization techniques
• Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
• Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
• Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification Cadence tool experience, lab test experience, and design experience at >10Gbps and in <28nm technologies are a plus
• MS or PhD in EE

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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