Principal Analog IC Design Engineer, High Speed SerDes

Cadence Design Systems; San Jose (CA); Hybrid; USD 137,000 - 254,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence Design Systems in SAN JOSE seeks a Principal Analog IC Design Engineer focused on high-speed SerDes. You will lead the design and development of analog/mixed-signal blocks from concept to verification in advanced CMOS processes, collaborating with cross-functional teams to meet customer specifications.

Requirements include 7+ years in CMOS SerDes or high-speed I/O, deep knowledge of jitter and equalization, and hands-on CAD tool proficiency.

Qualifications

• 7+ years of CMOS SerDes or high-speed I/O IC design experience.
• Working knowledge of SerDes standards and electrical requirements.
• Thorough understanding of jitter and signal equalization techniques.
• Proficient with CAD tools for circuit simulation, layout and verification.
• Experience with Cadence tool suite and lab testing a plus.

Responsibilities

• Design and develop analog/mixed-signal IC blocks from concept/specification through verification.
• Lead block-level design including Driver, Receiver, Serializer/Deserializer, PLL, clock distribution, and regulators.
• Collaborate with cross-functional teams to meet customer specifications.

Job description

## Principal Analog IC Design Engineer, High Speed SerDesApplylocations: SAN JOSEtime type: Full timeposted on: Posted Todayjob requisition id: R55853## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.* Candidate’s background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.* Working knowledge of a set of common SerDes standards and their electrical requirements is a plus.* Must have a thorough understanding of jitter and signal equalization techniques* Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators* Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment* Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification* Cadence tool experience, lab test experience, and design experience at >10Gbps and in <28nm technologies are a plus* MS or PhD in EE*The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*