Sr Principal Design Engineer

Cadence; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental and vision plan options

Job summary

Cadence in San Jose is seeking a skilled engineer to join their team focused on developing physical IP for high-speed serial-links. The ideal candidate will have a strong background in mixed-signal design and verification with a Ph.D. or MS in Electrical Engineering and significant industry experience.

The position offers an annual salary range of $154,000 to $286,000, along with potential bonuses and benefits including a 401(k) plan, paid vacation, and various medical options.

Qualifications

• Understanding of mixed-signal circuit design fundamentals is essential.
• Experience in mixed-signal design and verification flows required.
• Familiarity with Cadence analog design environment preferred.

Responsibilities

• Contribute to mixed-signal design, verification, and testing aspects.
• Execute post-silicon test plan development and collaborate with digital teams.

Skills

Mixed-signal circuit design fundamentals

Mixed-signal circuit design and verification flows

Cadence analog design environment

Basic signal processing concepts

Education

Ph.D. EE degree with 5+ years or MS EE degree with 7+ years

Tools

MATLAB

SystemVerilog

Perl

Python

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.

The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.

Candidate Must Have a Thorough Understanding Of The Following

• Mixed-signal circuit design fundamentals
• Mixed-signal circuit design and verification flows
• Cadence analog design environment
• Basic signal processing concepts

Familiarity With The Following Items Is a Plus

• Serial link design techniques
• Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
• MATLAB or C to facilitate architecture development
• Hardware description languages such as SystemVerilog or VerilogA for functional model development
• Scripting languages such as Perl or Python for automation
• Silicon validation testing knowledge and experience

Other Requirements

• Excellent verbal and written communication skills
• Ph.D. EE degree with 5+ years or MS EE degree with 7+ years of mixed signal design industry experience in advanced process technologies

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.