Lead Analog IC Design Engineer

Cadence; San Jose (CA); On-site; USD 119,000 - 221,000; Full time

Benefits offered by this job

401(k) plan with employer match

Medical, dental and vision plans

Paid vacation and holidays

Job summary

Cadence seeks a Lead Analog IC Design Engineer in California to drive analog and mixed-signal circuits from concept to final verification, ensuring compliance with customer requirements and industry standards. You will lead CMOS SerDes and high-speed I/O blocks, mentor engineers, and collaborate with cross-functional teams to deliver robust, high-performance designs for cutting-edge applications.

Strong communication, problem-solving, and knowledge of jitter/clocking are essential.

Qualifications

• 3+ years designing CMOS SerDes or high-speed I/O ICs.
• Experience with SerDes blocks: TX/RX, serializers/deserializers, PLLs, clock distribution, bias circuits.
• Understanding of jitter and signal-equalization techniques.
• Proficiency with CAD tools for circuit simulation, layout, and verification.
• Master’s or Ph.D. in Electrical Engineering.
• Strong problem-solving and communication; team player.

Responsibilities

• Lead analog IC design from concept through verification to meet customer specs.
• Collaborate with cross-functional teams to ensure design success.
• Mentor junior engineers and contribute to design reviews.

Skills

CMOS SerDes design

analog/mixed-signal design

CAD tools for circuit simulation

team collaboration

communication skills

high-speed I/O knowledge

Education

Master’s degree or Ph.D. in electrical engineering

Tools

Cadence design tools

circuit simulation tools

layout verification tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Role Overview

The Lead Analog IC Design Engineer is responsible for designing and developing analog and mixed-signal circuits- from initial concept and specification through final verification- to ensure conformance with customer requirements.

Required Qualifications

• At least three years of experience designing and developing CMOS SerDes or high-speed I/O integrated circuits.
• Design experience with most of the following SerDes circuit blocks: Transmitters and receivers, serializers and deserializers, phase interpolators, low-jitter PLLs, high-speed clock-distribution circuits, bias circuits, and voltage regulators.
• Good understanding of jitter and signal-equalization techniques.
• Proficiency with CAD tools for circuit simulation, layout, and physical verification.
• Master’s degree or Ph.D. in electrical engineering.
• Strong problem-solving skills and analog design aptitude.Clear written and verbal communication skills.
• Ability to collaborate effectively in a team environment.

Preferred Qualifications

• Working knowledge of common SerDes standards and their electrical requirements.
• Experience with Cadence design tools and laboratory testing.
• Design experience at data rates above 10 Gbps and in process technologies below 28 nm.

The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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