Senior Analog IC Designer – SerDes & High-Speed

Cadence Design Systems, Inc.; San Jose (CA); Vor Ort; USD 80.000 - 148.000; Vollzeit

Zusammenfassung

Cadence Design Systems, Inc. in Canada seeks a Principal Analog IC Designer to lead the development of analog/mixed-signal blocks, contributing to long-reach SerDes from concept to verification.

The role demands strong problem-solving, collaboration, and deep experience in CMOS SerDes and high-speed I/O. Candidates should have 5+ years in SerDes, jitter and equalization knowledge, proficiency with Cadence tools, and a degree (MS or PhD) in EE; experience at ≥16Gbps and ≤16nm is a plus.

Qualifikationen

• Minimum 5 years of experience in CMOS SerDes or high-speed I/O IC development.
• Thorough understanding of jitter and signal equalization techniques.
• Experience with SerDes blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, PLL, clock distribution, ADC/DAC, Bandgap and voltage regulators.
• Strong problem-solving and communication skills; ability to work in a team.
• Working knowledge of SerDes standards and electrical requirements.
• Proficiency with CAD tools for circuit simulation and post-layout verification; layout entry a plus.
• Cadence tool experience, lab tests, and designs at ≥16Gbps and ≤16nm are a plus.
• MS or PhD in EE.

Kenntnisse

CMOS SerDes

High-speed I/O

Jitter control

Signal equalization

Driver

Receiver

Serializer

Deserializer

Phase Interpolator

PLL

Clock distribution

ADC/DAC

Bandgap

Voltage regulators

Cadence

Lab tests

16Gbps

16nm

Ausbildung

MS in EE

PhD in EE

Tools

Cadence

Post-layout verification

Circuit simulation

Layout entry

Jobbeschreibung

Cadence Design Systems, Inc. in Canada seeks a Principal Analog IC Designer to lead the development of analog/mixed-signal blocks, contributing to long-reach SerDes from concept to verification.

The role demands strong problem-solving, collaboration, and deep experience in CMOS SerDes and high-speed I/O. Candidates should have 5+ years in SerDes, jitter and equalization knowledge, proficiency with Cadence tools, and a degree (MS or PhD) in EE; experience at ≥16Gbps and ≤16nm is a plus.