Sr Principal Design Engineer

Cadence; Cary (NC); On-site; USD 140,000 - 240,000; Full time

Job summary

Cadence is seeking a driven engineer to join a team developing physical IP for high-speed serial-links. You will lead mixed-signal design, verification, and testing from architecture through post-silicon validation, working with the digital team to ensure performance closure.

Ideal candidates have PhD or MS in EE with extensive experience in advanced processes, strong communication skills, and the ability to work independently on complex tasks.

Qualifications

• Ph.D. EE with 5+ years or MS EE with 7+ years of mixed-signal design industry experience in advanced process technologies.

Responsibilities

• Contribute to all mixed-signal design, verification, and testing aspects.
• Develop circuit design and development from high-level architectural specs.
• Create post-silicon test plans and lead execution with the digital team.
• Collaborate to achieve functional and performance closure.

Skills

Mixed-signal design

Design verification

Cadence tools

Signal processing basics

Education

PhD in EE

MS in EE

Tools

MATLAB

C

SystemVerilog

VerilogA

Python

Perl

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We offer amazing opportunities to grow, no matter where you are in your career.

This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.

The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.

Candidate Must Have a Thorough Understanding Of The Following

• Mixed-signal circuit design fundamentals
• Mixed-signal circuit design and verification flows
• Cadence analog design environment
• Basic signal processing concepts

Familiarity With The Following Items Is a Plus

• Serial link design techniques
• Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
• MATLAB or C to facilitate architecture development
• Hardware description languages such as SystemVerilog or VerilogA for functional model development
• Scripting languages such as Perl or Python for automation
• Silicon validation testing knowledge and experience

Other Requirements

• Excellent verbal and written communication skills
• Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.

We’re doing work that matters. Help us solve what others can’t.