Head of Advanced Packaging and Chiplet Integration

Jobtailor

Arizona

On-site

USD 170,000 - 250,000

Full time

5 days ago

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Job summary

Jobtailor seeks a leader to drive advanced packaging integration research in the United States. You will guide a multidisciplinary team to translate system requirements into robust package solutions, focusing on heterogeneous integration, chiplets, 2.5D/3DIC, and wafer-level packaging.

You will define strategy, roadmaps, milestones, and decision criteria aligned to product scaling. The role requires collaboration with silicon design, substrates, assembly, reliability, and manufacturing teams,

Qualifications

Demonstrated experience leading advanced technology research programs, multidisciplinary technical teams, cross-functional initiatives, or external research collaborations.
Ability to convert ambiguous integration challenges into clear hypotheses, experimental plans, measurable milestones, technology readiness criteria, and actionable recommendations.
Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability trade-offs.
Strong communication skills with the ability to present complex technical findings, integration trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.
Master’s degree in electrical engineering, Mechanical Engineering, Materials Science, Chemical Engineering, Applied Physics, Microelectronics, Semiconductor Manufacturing, or related engineering/science discipline; Ph.D. preferred.
Minimum of 7 years of experience in semiconductor technology roles.
Preferred experience in semiconductor packaging integration, heterogeneous integration, chiplet architectures, 2.5D/3DIC, hybrid bonding, interposer technology, or package-system co-optimization.

Responsibilities

Lead advanced packaging integration research programs and multidisciplinary teams.
Define integration strategy, roadmaps, milestones, and decision criteria aligned to product scaling needs.
Partner with silicon design, substrates, assembly, reliability, thermal, and manufacturing teams to close cross-domain gaps.
Translate system requirements into package integration solutions balancing performance, power, area, latency, bandwidth, thermal behavior, reliability, and manufacturability.
Drive feasibility studies, architecture trade-offs, process module evaluation, design rule development, prototyping, and experimental validation.
Lead technology readiness assessments, integration risk reviews, failure analysis learning cycles, reliability evaluations, and manufacturing feasibility reviews.
Drive intellectual property, technical publications, competitive benchmarking, and internal knowledge transfer.
Guide research-to-development transfer by defining integration requirements, qualification gaps, process control needs, manufacturability risks, cost implications, and scaling paths.
Communicate progress, trade-offs, risks, investment needs, and strategic recommendations to senior technical and business leaders.
Collaborate with universities, consortia, suppliers, equipment vendors, research labs, OSATs, foundry partners, design teams, and customer technology teams.