HBM SoC Physical Design Engineer — PPA & Tape-out Ready

Micron Technology, Inc.; Folsom (CA); On-site; USD 103,000 - 210,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and holidays

Retirement/benefits guidance

Job summary

Micron Technology, Inc. is seeking a SoC Physical Design Engineer in the Heterogeneous Integration Group to drive implementation from netlist to GDSII and ensure top‑level integration across products.

You will collaborate with RTL, verification, DFT, IP, packaging and manufacturing teams to optimize PPA and meet tape‑out milestones while enabling AI‑driven workflows in PD methodologies.

Qualifications

• 3+ years of relevant experience in SoC physical design.
• Proficiency with Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime and Calibre.
• Strong STA fundamentals and clocking/constraints (SDC).
• Experience with UPF/CPF power delivery and power integrity.
• Familiarity with DRC/LVS/ERC and sign-off workflows.

Responsibilities

• Own physical implementation for SoC blocks/top‑level, including floorplanning, placement, CTS, routing and optimization.
• Drive timing closure across MMMC scenarios with cross‑team coordination.
• Integrate IP with focus on robust physical integration and timing/power integrity.
• Coordinate physical signoff including DRC/LVS, IR drop/EM, and timing signoff.
• Collaborate with DFT, packaging, and manufacturing to ensure manufacturability.
• Support tape‑out and post‑silicon debug with PD/STA/power analysis.
• Identify flow gaps and drive automation improvements.

Skills

SoC physical design implementation

EDA tools proficiency

STA fundamentals

Power integrity concepts (UPF/CPF)

Physical verification basics (DRC/LVS/

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Cadence Innovus/Tempus

Synopsys ICC2/PrimeTime

Siemens Calibre

Job description

Micron Technology, Inc. is seeking a SoC Physical Design Engineer in the Heterogeneous Integration Group to drive implementation from netlist to GDSII and ensure top‑level integration across products.

You will collaborate with RTL, verification, DFT, IP, packaging and manufacturing teams to optimize PPA and meet tape‑out milestones while enabling AI‑driven workflows in PD methodologies.