HBM SoC Physical Design Engineer - Lead Tape-Out & PPA

Micron Technology, Inc.; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off and paid holidays

Benefit programs and retirement plans

Job summary

Micron Technology, Inc. in Richardson, Texas is seeking a hands-on HBM/SoC Physical Design Engineer to drive implementation from netlist to GDSII.

You will own blocks or top-level integration, manage floorplanning, placement, CTS, routing, and timing closure across MMMC scenarios. The role requires strong experience with EDA tools (Cadence Innovus, Tempus; Synopsys ICC2, PrimeTime; Calibre) and a solid grasp of power delivery, IP integration, and signoff.

Qualifications

• Experience in SoC physical design implementation from netlist to GDSII on advanced nodes.
• Proficiency with industry EDA tools (Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Calibre).
• Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques.
• Experience with power intent and power delivery considerations (UPF/CPF, power grid planning).
• Familiarity with physical verification/signoff concepts: DRC, LVS, timing signoff.

Responsibilities

• Own physical implementation for SoC blocks/top-level, including floorplanning, placement, CTS, routing, and optimization.
• Drive timing closure across multi-mode/multi-corner scenarios; collaborate with RTL, architecture, and STA signoff teams.

Skills

SoC physical design

EDA tools

STA fundamentals

Power integrity

Physical verification concepts

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Cadence Innovus

Tempus

Synopsys ICC2

PrimeTime

Calibre

Job description

Micron Technology, Inc. in Richardson, Texas is seeking a hands-on HBM/SoC Physical Design Engineer to drive implementation from netlist to GDSII.

You will own blocks or top-level integration, manage floorplanning, placement, CTS, routing, and timing closure across MMMC scenarios. The role requires strong experience with EDA tools (Cadence Innovus, Tempus; Synopsys ICC2, PrimeTime; Calibre) and a solid grasp of power delivery, IP integration, and signoff.