HBM SoC RTL Design Engineer: High-Performance AI Chips

Micron Technology; Folsom (CA); On-site; USD 121,000 - 247,000; Full time

Job summary

Micron Technology is seeking a SoC Design Engineer to join the Heterogeneous Integration Group in California. You will design RTL for SoC-level blocks in HBM logic die and integrate IP, collaborating with architecture, verification, and physical design teams to meet power, performance, and schedule targets.

You will also help enable AI-driven tools and workflows, participate in pre- and post-silicon bring-up, and contribute to design documentation and reviews to ensure robust, manufacturable

Qualifications

• Bachelor's or master's degree in electrical engineering or related field with 6+ years of experience.
• Proficiency in SystemVerilog/Verilog and SoC integration.
• Experience with RTL-to-GDS flow: synthesis, STA, sign-off.
• Familiarity with Cadence, Synopsys, and/or Siemens EDA tools.
• Programming or scripting experience (Python, TCL, Perl, or shell).

Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems in HBM logic die.
• Integrate internal and third-party IP (controllers, microcontrollers, NOC, RAS, MBIST, interfaces).
• Collaborate with SoC architects to translate specifications into RTL implementations.
• Participate in SoC-level integration activities (clocking, reset, power-intent).
• Assist with pre-silicon validation and post-silicon bring-up, root-cause analysis.
• Contribute to design documentation, block specs, and reviews.
• Collaborate with Product Eng, Test, Process Integration, and Manufacturing.

Skills

SystemVerilog

RTL integration

Python scripting

Shell scripting

Education

Bachelor/Master in EE/CE

Tools

Cadence tools

Synopsys tools

Siemens tools

Job description

Micron Technology is seeking a SoC Design Engineer to join the Heterogeneous Integration Group in California. You will design RTL for SoC-level blocks in HBM logic die and integrate IP, collaborating with architecture, verification, and physical design teams to meet power, performance, and schedule targets.

You will also help enable AI-driven tools and workflows, participate in pre- and post-silicon bring-up, and contribute to design documentation and reviews to ensure robust, manufacturable