HBM SoC Physical Design Engineer — PPA Master

Micron Memory Malaysia Sdn Bhd; Richardson (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Micron Technology in Richardson, TX, seeks a SoC Physical Design Engineer to lead physical implementation from netlist to GDSII for advanced HBM/DRAM‑adjacent designs. You will work with RTL, verification, DFT, IP, packaging and manufacturing to optimize PPA and ensure robust tape-out.

Responsibilities include floorplanning, placement, CTS, routing, clocking and signoff coordination, with a focus on power integrity and resistance to variations.

Qualifications

• Experience in SoC physical design implementation from netlist to GDSII.
• Proficiency with timing closure, DRC/LVS, and parasitic extraction concepts.

Responsibilities

• Own physical implementation for SoC blocks/top-level to meet PPA targets.
• Drive MMMC timing closure across multiple modes/corners.
• Coordinate IP integration and robust physical signoff (DRC/LVS/IR drop).
• Collaborate with DFT, packaging, and manufacturing to ensure tape-out readiness.
• Develop automation/scripts to improve PD flow.

Skills

SoC Physical Design

Floorplanning

Placement & CTS

Routing & Signoff

STA & timing closure

Power integrity

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s preferred

Tools

Cadence Innovus

Synopsys ICC2/PrimeTime

Calibre

Tempus

Job description

Micron Technology in Richardson, TX, seeks a SoC Physical Design Engineer to lead physical implementation from netlist to GDSII for advanced HBM/DRAM‑adjacent designs. You will work with RTL, verification, DFT, IP, packaging and manufacturing to optimize PPA and ensure robust tape-out.

Responsibilities include floorplanning, placement, CTS, routing, clocking and signoff coordination, with a focus on power integrity and resistance to variations.